1. Technical Field
This invention relates generally to charge pump circuits, and more particularly, but not exclusively, to charge pumps with improved linearity.
2. Description of the Related Art
Phase locked loops (PLLs) operate on the phase difference between a reference (crystal) clock and an oscillation (VCO) clock. A charge pump (CP) outputs a current to a loop filter that is proportional to the phase difference between these two clocks. In the locked state, the voltage at the charge pump output is a DC value that allows the VCO to oscillate at the desired frequency, because the loop filter suppresses the high-frequency components of the charge pump output.
However, nonlinearity in a phase frequency detector and CP results in higher noise and possibly spurious content in the VCO output spectrum, thereby affecting the PLL's accuracy. In the case of fractional-N PLLs, the nonlinearity folds modulation noise from a delta sigma modulator back into the loop filter bandwidth. Linearity in a CP is generally limited by power consumption.
Accordingly, a new CP is needed is that decreases nonlinearity without a significant increase in power consumption, thereby improving phase noise of the output clock.